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this document is a general product descripti on and is subject to change without notice. hynix semiconductor does not assume any responsibility for use of circuits described. no pat ent licenses are implied. rev. 0.2 / sep. 2008 1 200pin unbuffered ddr2 sdram so-d imms based on 2gb version a this hynix unbuffered small outline dual in-line memory module (dimm) series consists of 2gb version a ddr2 sdrams in fine ball grid array (fbga) packages on a 200 pin glass-epoxy substrate. this hynix 2gb version a based unbuffered ddr2 so-dimm series provide a high performance 8 byte interface in 67.60mm width form factor of indus- try standard. it is suitable for easy interchange and addition. features ordering information part name density organization # of drams # of ranks materials hmp451s6mmp8c- y5/s6 4gb 512mx64 16 2 lead free ? jedec standard double data rate 2 synchronous drams (ddr2 sdrams) with 1.8v +/- 0.1v power supply ? all inputs and outputs are compatible with sstl_1.8 interface ?posted cas ? programmable cas latency 3,4,5, and 6 ? ocd (off-chip driver impedance adjustment) and odt (on-die termination) ? fully differential clock operations (ck & ck ) ? programmable burst length 4 / 8 with both sequential and interleave mode ? auto refresh and self refresh supported ? 8192 refresh cycles / 64ms ? serial presence detect with eeprom ? ddr2 sdram package: 63 ball(x4/x8) ? 67.60 x 30.00 mm form factor ?rohs compliant
rev. 0.2 / sep. 2008 2 1 200pin unbuffered ddr2 sdram so-dimms speed grade & key parameters address table y5 (ddr2-667) s6 (ddr2-800) unit speed@cl3 400 - mbps speed@cl4 533 533 mbps speed@cl5 667 667 mbps speed@cl6 - 800 mbps cl-trcd-trp 5-5-5 6-6-6 tck density organization ranks sdrams # of drams # of row/bank/column address refresh method 4gb 512m x 64 2 256mb x 8 16 15(a0~a14)/3(ba0~ba2)/10(a0~a9) 8k / 64ms
rev. 0.2 / sep. 2008 3 1 200pin unbuffered ddr2 sdram so-dimms pin description symbol type polarity pin description ck[1:0], ck [1:0] input cross point the system clock inputs. all adress an comm ands lines are sampled on the cross point of the rising edge of ck and falling edge of ck . a delay locked loop(dll) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. cke[1:0] input active high activates the ddr2 sdram ck signal when high and deactivates the ck signal when low. by deactivating the clocks, cke low initiates the power down mode or the self refresh mode. s [1:0] input active low enables the associated ddr2 sdram comm and decoder when low and disables the command decoder when high. when the co mmand decoder is disabled, new commands are ignored but previous operations continue. rank 0 is selected by s 0; rank 1 is selected by s 1 ras , cas , we input active low when sampled at the cross point of the rising edge of ck and falling edge of ck , cas , ras and we define the operation to be executed by the sdram. ba[2:0] input selects which ddr2 sdram intern al bank of four or eight is activated. odt[1:0] input active high asserts on-die termination for dq, dm, dqs and dqs signals if enab led via the ddr2 sdram mode register. a[9:0], a10/ap, a[15:11] input during a bank activate command cycle, defines the row address when sampled at the cross point of the rising edge of ck and falling edge of ck . during a read or write com- mand cycle, defines the column address when sampled at the cross point of the rising edge of ck and falling edge of ck . in addition to the column address, ap is used to invoke autoprecharge operation at the end of the burst read or write cycle. if ap is high., autoprecharge is selected and ba0-ban defines the bank to be precharged. if ap is low, autoprecharge is disabled. during a precharge command cycle., ap is used in conjunction with ba0-ban to control which bank(s) to precharge. if ap is high, all banks will be precharged regardless of the state of ba0-ban inputs. if ap is low, then ba0-ban are used to define which bank to precharge. dq[63:0] in/out data input/output pins. dm[7:0] input active high the data write masks, associated with one da ta byte. in write mode, dm operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. in read mode, dm lines have no effect. dqs[7:0], dqs [7:0] in/out cross point the data strobe, associated with one data byte, sourced whit data transfers. in write mode, the data strobe is sourced by the controller and is centered in the data window. in read mode, the data strobe is sourced by the ddr2 sdrams and is sent at leading edge of the data window. dqs signals are complements, and timing is relative to the crosspoint of respective dqs and dqs . if the module is to be operated in single ended strobe mode, all dqs signals must be tied on the system board to vss and ddr2 sdram mode registers programmed approriately. v dd , v dd spd,v ss supply power supplies for core, i/o, serial presence detect, and ground for the module. sda in/out this is a bidirectional pin used to transfer data into or out of the spd eeprom. a resister must be connected to v dd t o act as a pull up. scl input this signals is used to clock data into and out of the spd eeprom. a resistor may be connected from scl to vd d to act as a pull up. sa[1:0] input address pins used to select the serial presence detect base address. test in/out the test pin is reserved for bus analysis to ols and is not connected on normal memory modules(sodimms).
rev. 0.2 / sep. 2008 4 1 200pin unbuffered ddr2 sdram so-dimms pin assignment pin location pin no. front side pin no. back side pin no. front side pin no. back side pin no. front side pin no. back side pin no. front side pin no. back side 1 vref 2 vss 51 dqs2 52 dm2 101 a1 102 a0 151 dq42 152 dq46 3 vss 4 dq4 53 vss 54 vss 103 vdd 104 vdd 153 dq43 154 dq47 5 dq0 6 dq5 55 dq18 56 dq22 105 a10/ap 106 ba1 155 vss 156 vss 7 dq1 8 vss 57 dq19 58 dq23 107 ba0 108 ras 157 dq48 158 dq52 9 vss 10 dm0 59 vss 60 vss 109 we 110 s 0 159 dq49 160 dq53 11 dqs 0 12 vss 61 dq24 62 dq28 111 vdd 112 vdd 161 vss 162 vss 13 dqs0 14 dq6 63 dq25 64 dq29 113 cas 114 odt0 163 nc,test 164 ck1 15 vss 16 dq7 65 vss 66 vss 115 nc/s 1 116 a13 165 vss 166 ck 1 17 dq2 18 vss 67 dm3 68 dqs 3 117 vdd 118 vdd 167 dqs 6 168 vss 19 dq3 20 dq12 69 nc 70 dqs3 119 nc/odt1 120 nc 169 dqs6 170 dm6 21 vss 22 dq13 71 vss 72 vss 121 vss 122 vss 171 vss 172 vss 23 dq8 24 vss 73 dq26 74 dq30 123 dq32 124 dq36 173 dq50 174 dq54 25 dq9 26 dm1 75 dq27 76 dq31 125 dq33 126 dq37 175 dq51 176 dq55 27 vss 28 vss 77 vss 78 vss 127 vss 128 vss 177 vss 178 vss 29 dqs 1 30 ck0 79 cke0 80 nc/cke1 129 dqs 4 130 dm4 179 dq56 180 dq60 31 dqs1 32 ck 0 81 vdd 82 vdd 131 dqs4 132 vss 181 dq57 182 dq61 33 vss 34 vss 83 nc 84 nc/a15 133 vss 134 dq38 183 vss 184 vss 35 dq10 36 dq14 85 ba2 86 nc/a14 135 dq34 136 dq39 185 dm7 186 dqs 7 37 dq11 38 dq15 87 vdd 88 vdd 137 dq35 138 vss 187 vss 188 dqs7 39 vss 40 vss 89 a12 90 a11 139 vss 140 dq44 189 dq58 190 vss 41 vss 42 vss 91 a9 92 a7 141 dq40 142 dq45 191 dq59 192 dq62 43 dq16 44 dq20 93 a8 94 a6 143 dq41 144 vss 193 vss 194 dq63 45 dq17 46 dq21 95 vdd 96 vdd 145 vss 146 dqs 5 195 sda 196 vss 47 vss 48 vss 97 a5 98 a4 147 dm5 148 dqs5 197 scl 198 sa0 49 dqs 2 50 nc 99 a3 100 a2 149 vss 150 vss 199 vddspd 200 sa1 front side pin #1 pin #39 pin #41 pin #99 back side pin #2 pin #40 pin #42 pin #200
rev. 0.2 / sep. 2008 5 1 200pin unbuffered ddr2 sdram so-dimms functional block diagram 4gb(512mbx64): hmp451s6mmp8c dq0 cke1 dqs0 /dqs0 dm0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 5 i/o 6 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 /cs0 i/o 7 d0 dqs /dqs dm odt1 /s0 3 ? +/-5% odt0 cke0 /s1 odt0 cke0 i/o 5 i/o 6 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 /cs1 i/o 7 d8 dqs /dqs dm odt1 cke1 dq8 dqs1 /dqs1 dm1 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 5 i/o 6 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 /cs0 i/o 7 d2 dqs /dqs dm odt0 cke0 i/o 5 i/o 6 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 /cs1 i/o 7 d10 dqs /dqs dm odt1 cke1 dq16 dqs2 /dqs2 dm2 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 5 i/o 6 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 /cs0 i/o 7 d4 dqs /dqs dm odt0 cke0 i/o 5 i/o 6 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 /cs1 i/o 7 d12 dqs /dqs dm odt1 cke1 dq24 dqs3 /dqs3 dm3 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 5 i/o 6 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 /cs0 i/o 7 d6 dqs /dqs dm odt0 cke0 i/o 5 i/o 6 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 /cs1 i/o 7 d14 dqs /dqs dm odt1 cke1 dq32 dqs4 /dqs4 dm4 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 5 i/o 6 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 /cs0 i/o 7 d1 dqs /dqs dm odt0 cke0 i/o 5 i/o 6 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 /cs1 i/o 7 d9 dqs /dqs dm odt1 cke1 dq40 dqs5 /dqs5 dm5 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 5 i/o 6 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 /cs0 i/o 7 d3 dqs /dqs dm odt0 cke0 i/o 5 i/o 6 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 /cs1 i/o 7 d11 dqs /dqs dm odt1 cke1 dq48 dqs6 /dqs6 dm6 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o 5 i/o 6 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 /cs0 i/o 7 d5 dqs /dqs dm odt0 cke0 i/o 5 i/o 6 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 /cs1 i/o 7 d13 dqs /dqs dm odt1 cke1 dq56 dqs7 /dqs7 dm7 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 5 i/o 6 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 /cs0 i/o 7 d7 dqs /dqs dm odt0 cke0 i/o 5 i/o 6 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 /cs1 i/o 7 d15 dqs /dqs dm odt1 cke1 ba0-ba2 a0-an /ras /cas /we sdrams d0-15 sdrams d0-15 sdrams d0-15 sdrams d0-15 sdrams d0-15 ck0 /ck0 8 loads ck1 /ck1 8 loads sda scl wp a0 a1 a2 serial pd scl sda sa0 sa1 v ref v dd v dd spd serial pd v ss sdrams d0-d15, spd sdrams d0-d15, v dd and v dd q sdrams d0-d15 note: 1.resistor values are 22 ohm +/-5% unless otherwide stated. 10 ? +/-5% 5.6pf 5.6pf
rev. 0.2 / sep. 2008 6 1 200pin unbuffered ddr2 sdram so-dimms absolute maximum ratings operating conditi ons and environmental parameters notes: 1. stress greater than those listed may cause permanent dama ge to the device. this is a stress rating only, and device functional operation at or above the conditions indica ted is not implied. exposure to absolute maximum rating con ditions for extended periods may affect reliability. 2. up to 9850 ft. 3. if the dram case temperature is above 85 oc , the auto-refresh command inte rval has to be reduced to trefi=3.9us. for measurement conditions of tc ase, please refer to the jedec document jesd51-2. dc operating conditions (sstl_1.8) note: 1. min. type. and max. values increase by 100mv for c3(ddr2-533 3-3-3) speed option. 2. vddq tracks with vdd,vddl tracks with vdd. ac parameters are measured with vdd,vddq and vdd. 3. the value of vref may be selected by the user to pr ovide optimum noise margin in the system. typically the value of vref is expected to be about 0.5 x vddq of the transmitting device and vref is expected to track varia- tions in vddq. 4. peak to peak ac noise on vref may not exceed +/-2% vref (dc). 5. vtt of transmitting device must track vref of receiving device. parameter symbol value unit note voltage on v dd pin relative to vss v dd - 1.0 v ~ 2.3 v v 1 voltage on v ddq pin relative to vss v ddq - 0.5 v ~ 2.3 v v 1 voltage on vddl pin relative to vss vddl -0.5v ~ 2.3 v v 1 voltage on any pin relative to vss v in, v out - 0.5 v ~ 2.3 v v 1 parameter symbol rating units notes dimm operating temperature(ambient) t opr 0 ~ +65 o c storage temperature t stg -50 ~ +100 o c 1 storage humidity(without condensation) h stg 5 to 95 % 1 dimm barometric pressure(operating & storage) p bar 105 to 69 k pascal 2 dram component case temperature range t case 0 ~+95 o c 3 symbol parameter rating units notes min. typ. max. vdd supply voltage 1.7 1.8 1.9 v 1 vddl supply voltage for dll 1.7 1.8 1.9 v 1,2 vddq supply voltage for output 1.7 1.8 1.9 v 1,2 vref input reference voltage 0.49*vddq 0.50*vddq 0.51*vddq mv 3,4 vtt termination voltage vref-0.04 vref vref+0.04 v 5 vddspd eeprom supply voltage 1.8 - 3.3 v
rev. 0.2 / sep. 2008 7 1 200pin unbuffered ddr2 sdram so-dimms input dc logic level input ac logic level ac input test conditions notes : 1. input waveform timing is referenced to the input signal crossing through the v ref level applied to the device under test. 2. the input signal minimum slew rate is to be maintained over the range from v ref to v ih(ac) min for rising edges and the range from v ref to v il(ac) max for falling edges as shown in the below figure. 3. ac timings are referenced with input waveforms switchin g from vil(ac) to vih(ac) on the positive transitions and vih(ac) to vil(ac) on the negative transitions. parameter symbol min max unit note dc input logic high v ih (dc) v ref + 0.125 v ddq + 0.3 v dc input logic low v il (dc) -0.30 v ref - 0.125 v parameter symbol ddr2 667 ddr2 800 unit min max min max ac input logic high v ih (ac) v ref + 0.200 - v ref + 0.200 - v ac input logic low v il (ac) -v ref - 0.200 - v ref - 0.200 v symbol condition value units notes v ref input reference voltage 0.5 * v ddq v1 v swing(max) input signal maximum peak to peak swing 1.0 v 1 slew input signal minimum slew rate 1.0 v/ns 2, 3 v ddq v ih(ac) min v ih(dc) min v ref v il(dc) max v il(ac) max v ss v swing(max) delta tr delta tf v ref - v il (ac) max delta tf falling slew = rising slew = v ih (ac) min - v ref delta tr < figure: ac input test signal waveform>
rev. 0.2 / sep. 2008 8 1 200pin unbuffered ddr2 sdram so-dimms differential input ac logic level 1. v in (dc) specifies the allowable dc execution of each input of di fferential pair such as ck, ck , dqs, dqs , ldqs, ldqs , udqs and udqs . 2. v id (dc) specifies the input differential voltage |v tr -v cp | required for switching, where v tr is the true input (such as ck, dqs, ldqs or udqs) level and v cp is the complementary input (such as ck , dqs , ldqs or udqs ) level. the minimum value is equal to v ih (dc) - v il (dc). notes : 1. v id (ac) specifies the input differential voltage |v tr -v cp | required for switching, where v tr is the true input signal (such as ck, dqs, ldqs or udqs) and v cp is the complementary input signal (such as ck , dqs , ldqs or udqs ). the minimum value is equal to v ih (ac) - v il (ac). 2. the typical value of v ix (ac) is expected to be about 0.5 * v ddq of the transmitting device and v ix (ac) is expected to track variations in v ddq . v ix (ac) indicates the voltage at which differential input signals must cross. differential ac ou tput parameters notes: 1. the typical value of v ox (ac) is expected to be about 0.5 * v ddq of the transmitting device and v ox (ac) is expected to track variations in v ddq . v ox (ac) indicates the voltage at which differential output signals must cross. symbol parameter min. max. units note v id (ac) ac differential input voltage 0.5 v ddq + 0.6 v 1 v ix (ac) ac differential cr oss point voltage 0.5 * v ddq - 0.175 0.5 * v ddq + 0.175 v 2 symbol parameter min. max. units note v ox (ac) ac differential cross point voltage 0.5 * v ddq - 0.125 0.5 * v ddq + 0.125 v 1 crossing point v ssq v tr v cp v id v ix or v ox < differential signal levels >
rev. 0.2 / sep. 2008 9 1 200pin unbuffered ddr2 sdram so-dimms output buffer levels output ac test conditions notes: 1. the vddq of the device under test is referenced. output dc current drive notes: 1. v ddq = 1.7 v; v out = 1420 mv. (v out - v ddq )/i oh must be less than 21 ohm for values of v out between v ddq and v ddq - 280 mv. 2. v ddq = 1.7 v; v out = 280 mv. v out /i ol must be less than 21 ohm for values of v out between 0 v and 280 mv. 3. the dc value of v ref applied to the receiving device is set to v tt 4. the values of i oh (dc) and i ol (dc) are based on the conditions given in notes 1 and 2. they are used to test device drive current capability to ensure v ih min plus a noise margin and v il max minus a noise margin are delivered to an sstl_18 receiver. the actual current values are derived by shifting the de sired driver operating point along a 21 ohm load line to define a convenient driver current for measurement. symbol parameter sstl_18 units notes v otr output timing measurement reference level 0.5 * v ddq v1 symbol parameter sstl_18 units notes i oh(dc) output minimum source dc current - 13.4 ma 1, 3, 4 i ol(dc) output minimum sink dc current 13.4 ma 2, 3, 4
rev. 0.2 / sep. 2008 10 1 200pin unbuffered ddr2 sdram so-dimms pin capacitance (vdd=1.8v,vddq=1.8v, ta=25?) 4gb: hmp451s6mmp8c notes: 1. pins not under test are tied to gnd. 2. these value are guaranteed by design and tested on a sample basis only. pin symbol min max unit ck, ck cck 20 37 pf cke, odt,cs ci1 25 49 pf address, ras , cas , we ci2 32 61 pf dq, dm, dqs, dqs cio 8 13 pf
rev. 0.2 / sep. 2008 11 1 200pin unbuffered ddr2 sdram so-dimms idd specifications (t case : 0 to 95 o c) 4gb, 512m x 64 so-dimm: hmp451s6mmp8c notes: 1. idd6 current values are guaranteed up to tcase of 85c max. symbol y5 (ddr2 667@cl5) s5/s6 (ddr2 800@cl5&6) unit note idd0 2080 2080 ma idd1 2400 2400 ma idd2p 128 240 ma idd2q 720 720 ma idd2n 800 800 ma idd3p(f) 560 560 ma idd3p(s) 288 288 ma idd3n 880 880 ma idd4r 3520 3520 ma idd4w 3200 3200 ma idd5b 4480 4480 ma idd6 128 240 ma 1 idd6(l) 80 128 ma 1 idd7 5520 5520 ma
rev. 0.2 / sep. 2008 12 1 200pin unbuffered ddr2 sdram so-dimms idd measurement conditions notes: 1. idd specifications are tested afte r the device is properly initialized 2. input slew rate is specified by ac parametric test condition 3. idd parameters are s pecified with odt disabled. 4. data bus consists of dq, dm, dqs, dqs , rdqs, rdqs , ldqs, ldqs, udqs, and udqs . idd values must be met with all combina- tions of emrs bits 10 and 11. 5. definitions for idd low is defined as vin vilac(max) high is defined as vin ? vihac(min) stable is defined as inputs stable at a high or low level floating is defined as inputs at vref = vddq/2 switching is defined as: inputs changing between high and low every other clock cycle (once per two clocks) for address and control signals, and inputs changing between high and low every other data transfer ( once per clock) for dq signals not including masks or strobes. symbol conditions units idd0 operating one bank active-precharge current ; t ck = t ck(idd), t rc = t rc(idd), t ras = t ras- min(idd);cke is high, cs is high between valid commands;addres s bus inputs are switching;data bus inputs are switching ma idd1 operating one bank active-read-precharge current ; iout = 0ma;bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t rc = t rc (idd), t ras = t rasmin(idd), t rcd = t rcd(idd); cke is high, cs is high between valid commands; address bus inputs are switching; data pattern is same as idd4w ma idd2p precharge power-down current ; all banks idle; t ck = t ck(idd); cke is low; other control and address bus inputs are stable; data bus inputs are floating ma idd2q precharge quiet standby current ;all banks idle; t ck = t ck(idd);cke is high, cs is high; other control and address bus inputs are stable; data bus inputs are floating ma idd2n precharge standby current ; all banks idle; t ck = t ck(idd); cke is high, cs is high; other control and address bus inputs are switching; data bus inputs are switching ma idd3p active power-down current ; all banks open; t ck = t ck(idd); cke is low; other control and address bus inputs are stable; data bus inputs are float- ing fast pdn exit mrs(12) = 0 ma slow pdn exit mrs(12) = 1 ma idd3n active standby current ; all banks open; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs is high between valid commands; other control and address bus inputs ar e switching; data bus inputs are switching ma idd4w operating burst write current ; all banks open, continuous burst writes; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs is high between valid commands; address bus inputs are switching; data bus inputs are switching ma idd4r operating burst read current ; all banks open, continuous burst reads, iout = 0ma; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs is high between valid com- mands; address bus inputs are switching; data pattern is same as idd4w ma idd5b burst refresh current ; t ck = t ck(idd); refresh command at every t rfc(idd) interval; cke is high, cs is high between valid commands; other control and addres s bus inputs are switching; data bus inputs are switching ma idd6 self refresh current ; ck and ck at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating. idd6 current values are guaranteed up to tcase of 85 ? max. ma idd7 operating bank interleave read current ; all bank interleaving reads, iout = 0ma; bl = 4, cl = cl(idd), al = t rcd(idd)-1* t ck(idd); t ck = t ck(idd), t rc = t rc(idd), t rrd = t rrd(idd), t rcd = 1* t ck(idd); cke is high, cs is high between valid commands; address bus inputs are stable during deselects; data pattern is same as idd4r; - refer to the following page for detailed timing conditions ma
rev. 0.2 / sep. 2008 13 1 200pin unbuffered ddr2 sdram so-dimms electrical characteristics & ac timings speed bins and cl,trcd,trp,trc and tras for corresponding bin ac timing parameters by speed grade speed ddr2-800 (s5) ddr2-800 (s6) ddr2-667 (y5) unit bin(cl-trcd-trp) 5-5-5 6-6-6 5-5-5 parameter min min min cas latency 5 6 5 tck trcd 12.5 15 15 ns trp 12.5 15 15 ns tras 45 45 45 ns trc 57.5 60 60 ns parameter symbol ddr2-667 ddr2-800 unit note min max min max average clock period tck 3000 8000 2500 8000 ps 35,36 average clock high pulse width tch 0.48 0.52 0.48 0.52 tck 35,36 average clock low pulse width tcl 0.48 0.52 0.48 0.52 tck 35,36 write command to dqs associated clock edge wl rl-1 rl-1 rl-1 rl-1 nck dqs latching rising transition to associated clock edges tdqss -0.25 0.25 -0.25 0.25 tck 30 dqs falling edge to ck setup time tdss 0.2 x 0.2 x tck 30 dqs falling edge hold time from ck tdsh 0.2 x 0.2 x tck 30 dqs input high pulse width tdqsh 0.35 x 0.35 x tck dqs input low pulse width tdqsl 0.35 x 0.35 x tck write preamble twpre 0.35 x 0.35 x tck write postamble twpst 0.4 0.6 0.4 0.6 tck 10 address and control input setup time tls 200 x 175 x ps 5,7,9, 22,29 address and control input hold time tih 275 x 250 x ps 5,7,9, 22,29 control & address input pulse width for each input tlpw 0.6 x 0.6 x tck dq and dm input setup time tds 100 x 50 x ps 6,7,8, 20,28, 31 dq and dm input hold time tdh 175 x 125 x ps 6,7,8, 20,28, 31 dq and dm input pulse width for each input tdipw 0.35 x 0.35 x tck
rev. 0.2 / sep. 2008 14 1 200pin unbuffered ddr2 sdram so-dimms parameter symbol ddr2-667 ddr2-800 unit note min max min max dq output access time from ck/ck tac -450 +450 -400 +400 ps dqs output access time from ck/ck tdqsck -400 +400 -350 +350 ps ck high-level width tch 0.45 0.55 0.48 0.52 tck ck low-level width tcl 0.45 0.55 0.48 0.52 tck ck half period thp min(tcl, tch) - min(tcl, tch) - ps clock cycle time, cl=x tck 3000 8000 2500 8000 ps dq and dm input setup time (differential strobe) tds 100 - 50 - ps 1 dq and dm input hold time (differential strobe) tdh 175 - 125 - ps 1 control & address input pulse width for each input tipw 0.6 - 0.6 - tck dq and dm input pulse width for each input tdipw 0.35 - 0.35 - tck data-out high-impedance time from ck/ck thz - tac max tac max ps dqs low-impedance time from ck/ck tlz(dqs) tac min tac max tac min tac max ps dq low-impedance time from ck/ck tlz(dq) 2*tac min tac max 2*tac min tac max ps dqs-dq skew for dqs and associated dq signals tdqsq - 240 - 240 ps dq hold skew factor tqhs - 340 - 300 ps dq/dqs output hold time from dqs tqh thp - tqhs - thp - tqhs - ps first dqs latching trans ition to associated clock edge tdqss -0.25 +0.25 -0.25 +0.25 tck dqs input high pulse width tdqsh 0.35 - 0.35 - tck dqs input low pulse width tdqsl 0.35 - 0.35 - tck dqs falling edge to ck setup time tdss 0.2 - 0.2 - tck dqs falling edge hold time from ck tdsh 0.2 - 0.2 - tck mode register set command cycle time tmrd 2 - 2 - tck write preamble twpre 0.35 - 0.35 - tck write postamble twpst 0.4 0.6 0.4 0.6 tck address and control input setup time tis 200 - 175 - ps address and control input hold time tih 275 - 250 - ps read preamble trpre 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 tck activate to precharge command tras 45 70000 45 70000 ns row active to row active delay for 1kb page size trrd 7.5 - 7.5 - ns row active to row active delay for 2kb page size trrd 10 - 10 - ns four active window for 1kb page size products tfaw 37.5 - 35 - ns
rev. 0.2 / sep. 2008 15 1 200pin unbuffered ddr2 sdram so-dimms - continued - notes: 1. for details and notes, please refer to t he relevant hynix component datasheet(h5ps4g83mmp). 2. 0 c ? t case ? c 3. c # t case ? c parameter symbol ddr2-667 ddr2-800 unit note min max min max cas to cas command delay tccd 2 2 - tck write recovery time twr 15 - 15 - ns auto precharge write recovery + precharge time tdal wr+trp - wr+trp - tck internal write to read command delay twtr 7.5 - 7.5 - ns internal read to pr echarge command delay trtp 7.5 7.5 - ns exit self refresh to a non-read command txsnr trfc + 10 - trfc + 10 - ns exit self refresh to a read command txsrd 200 - 200 - tck exit precharge power down to any non- read command txp 2 - 2 - tck exit active power down to read command txard 2 - 2 - tck exit active power down to read command (slow exit, lower power) txards 7 - al - 8 - al - tck cke minimum pulse width (high and low pulse width) tcke 3 - 3 - tck odt turn-on delay taond 2 2 2 2 tck odt turn-on taon tac(min) tac(max)+0.7 tac(min) tac(max)+0.7 ns odt turn-on(power-down mode) taonpd tac(min)+2 2tck+ tac(max)+1 tac(min)+2 2tck+ tac(max)+1 ns odt turn-off delay taofd 2.5 2.5 2.5 2.5 tck odt turn-off taof tac(min) tac(max)+ 0.6 tac(min) tac(max)+ 0.6 ns odt turn-off (power-down mode) taofpd tac(min)+2 2.5tck+ tac(max)+1 tac(min)+2 2.5tck+ tac(max)+1 ns odt to power down entry latency tanpd 3 - 3 - tck odt power down exit latency taxpd 8 8 tck ocd drive mode output delay toit 0 12 0 12 ns minimum time clocks remains on after cke asynchronously drops low tdelay tis+tck+tih - tis+tck+tih - ns average periodic refresh interval trefi - 7.8 - 7.8 us 2 trefi - 3.9 - 3.9 us 3
rev. 0.2 / sep. 2008 16 1 200pin unbuffered ddr2 sdram so-dimms package outline 512mx64 - hymp451s6mmp8 front 67.60 2.00 min 4.00 +/-0.10 pin 1 pin 39 pin 41 pin 199 47.40 20.00 6.00 30.00 47.40 pin 2 pin 40 pin 42 pin 200 back note: 1. all dimensions are in millimeters. 2. all outline dimensions and tolerances follow the jedec standard. 4jef 3.8 max ? ? ? %fubjmpg$poubdut" %fubjmpg$poubdut# 'spou
? ? ? ? %fubjmpg$poubdut# #bdl
detail-b detail-b detail-a 11.40 1.80 ? 0.10 4.20 2.15 2.45 11.40 1.50 ? 0.10
rev. 0.2 / sep. 2008 17 1 200pin unbuffered ddr2 sdram so-dimms revision history revision history date 0.1 initial data sheet released may. 2008 0.2 editorial correction sep. 2008

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